The present invention relates to arrays for performing logic functions and more particularly it is related to an orderly arrangement of input and output lines for such arrays.
The performing of logic in an array of identical circuit elements each located at a unique intersection of an input and output line in a grid of intersecting input and output lines is well known. It is also well known to perform logic in a compound arrangement of these arrays called a programmable logic array chip (PLA) by using the outputs of one array as the inputs to another array. Co-pending U.S. patent application Ser. No. 537,219 filed on even date herewith describes such a PLA on which a number of decoders feed inputs to a first array called a product term generator or an AND array which in turn supplies outputs to a second array called a sum of product term generator or an OR array. The outputs of the OR array are then used to control the setting and resetting of a string of latches so that both combinatorial and sequential logic functions can be performed by the PLA. The particular logic functions actually performed by the given PLA are controlled by the locations and number of the active logic circuits in the AND and OR arrays of the PLA and also by how inputs are supplied to the decoders either from off the chip or from the latches. For this and other reasons the external connections to the decoders and latches change with the functions performed by the PLA. As a result, the advantages that array logic has in design and manufacturing of monolithic chips containing logic performing circuits cannot be fully realized unless the arrangement used in making the external connections to the arrays is flexible and effects a minimum number of processing steps in manufacturing of the monolithic chip.